What a Senior } should know

Implements optimized algorithms for MCU: fixed-point math, lookup tables, branch-free code. Profiles using cycle counter (DWT).

Designs async firmware architecture: coroutine-based approach, cooperative scheduling, zero-copy DMA pipelines. Minimizes ISR latency.

Introduces quality tools: MISRA compliance checking, code coverage for firmware, automated code review. Establishes quality gates for CI.

Designs custom data structures for embedded: lock-free queues for ISR, memory-mapped structures, packed structs for protocols.

Designs memory management strategy: MPU configuration, memory-mapped I/O, scatter-loading, placement in specific RAM sections (CCM, DTCM).

Designs concurrent firmware architecture: lock-free algorithms, ISR-safe communications, priority ceiling protocol. Minimizes critical sections.

Designs CI/CD platform for multiple projects. Creates reusable workflows/templates. Optimizes build time at organization level. Configures security scanning in pipeline. Introduces deployment strategies (blue-green, canary). Integrates with ArgoCD/FluxCD.

Designs test architecture for firmware: hardware abstraction for testability, test doubles for peripherals, property-based testing.

Conducts deep reviews: timing analysis, resource usage, safety implications. Mentors junior/middle engineers through reviews, creates review checklists.

Manages complex Git scenarios: monorepo for firmware + tools, git-bisect for regression hunting, Git LFS for binary assets.

Designs bare-metal architecture for production devices. Implements custom scheduler, power management, watchdog recovery, OTA update mechanism.

Designs BLE mesh networks and multi-connection architectures. Optimizes power consumption in BLE, implements OTA DFU, integrates BLE 5.3 features.

Designs HAL layer in C for MCU families. Optimizes code for Flash/RAM constraints, applies DMA and interrupts for high-performance tasks.

Designs zero-cost abstraction HAL in C++ with templates. Applies compile-time polymorphism, optimizes binary size through LTO and -fno-rtti.

Designs debug infrastructure: custom fault handlers, core dump extraction, post-mortem analysis. Applies Segger SystemView for RTOS profiling.

Designs analog data acquisition systems: oversampling, digital filtering, ADC calibration pipeline. Optimizes power consumption through GPIO configuration.

Designs MQTT architecture for IoT fleet: shared subscriptions, broker bridging, MQTT 5.0 features. Implements TLS and client certificate authentication.

Designs hard real-time systems with guaranteed deadlines. Applies formal timing analysis, optimizes interrupt latency, uses hardware timers.

Designs RTOS application architecture with guaranteed response time. Optimizes stack allocation, applies priority inversion protection, configures tickless idle.

Designs high-performance communications: multi-slave SPI with chip select mux, I2C bus recovery, UART with custom protocol and CRC.

Designs CPU profiling infrastructure: continuous performance monitoring, automated regression benchmarks, power/performance correlation analysis.

Designs ultra-low latency systems: deterministic ISR, zero-wait-state memory access, DMA chaining, predictable scheduling.

Designs resource-efficient firmware: function-level power management, adaptive clock scaling, memory overlay techniques.