Algorithms & Data Structures 2
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Understands O-notation and basic algorithms in embedded context: sorting, searching considering MCU memory constraints. Selects appropriate algorithms.
Applies algorithm optimization for embedded: fixed-point arithmetic, lookup tables instead of computation, loop unrolling. Analyzes time complexity considering cache effects.
Implements optimized algorithms for MCU: fixed-point math, lookup tables, branch-free code. Profiles using cycle counter (DWT).
Defines algorithmic standards for the embedded platform. Establishes optimized algorithm library, conducts critical path reviews.
Knows basic data structures for embedded: arrays, linked lists, queues. Understands dynamic memory limitations on MCU.
Implements data structures for embedded: statically-allocated ring buffers, memory pools, intrusive linked lists. Optimizes for cache locality and deterministic performance.
Designs custom data structures for embedded: lock-free queues for ISR, memory-mapped structures, packed structs for protocols.
Defines data structure standards for the embedded platform. Establishes statically-allocated container library, conducts reviews.
CI/CD 1
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Understands CI/CD concepts for embedded development: build, test, deploy for firmware. Uses existing workflows for cross-compilation and hardware-in-the-loop tests. Can add a step for firmware validation. Reads failed build logs for toolchain issues.
Designs CI/CD pipelines from scratch. Configures caching to speed up builds. Uses matrix builds for testing on different versions. Sets up deployment pipelines (staging → production). Works with secrets and environment variables.
Designs CI/CD platform for multiple projects. Creates reusable workflows/templates. Optimizes build time at organization level. Configures security scanning in pipeline. Introduces deployment strategies (blue-green, canary). Integrates with ArgoCD/FluxCD.
Clean Code & Refactoring 1
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Follows coding standards: variable naming, formatting, commenting in embedded C/C++. Uses clang-format for consistency.
Maintains embedded code quality: static analysis (PC-lint, Coverity), MISRA C compliance checking, complexity metrics. Configures quality gates in CI.
Introduces quality tools: MISRA compliance checking, code coverage for firmware, automated code review. Establishes quality gates for CI.
Defines code quality strategy for the embedded team. Establishes MISRA compliance process, conducts architecture reviews.
Code Review 1
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Participates in code review: checks formatting, naming. Learns to give constructive feedback on embedded code.
Reviews embedded code: checks memory safety, interrupt correctness, peripheral configuration. Gives well-reasoned feedback.
Conducts deep reviews: timing analysis, resource usage, safety implications. Mentors junior/middle engineers through reviews, creates review checklists.
Defines code review standards for the team. Establishes review checklist for safety-critical embedded, conducts architecture reviews.
Concurrency & Parallelism 2
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Understands async model in embedded: interrupts, callbacks, event-driven architecture. Implements simple ISR handlers on STM32.
Implements async patterns in embedded: interrupt-driven I/O, DMA completion callbacks, event-driven state machines. Manages shared state between ISR and main loop.
Designs async firmware architecture: coroutine-based approach, cooperative scheduling, zero-copy DMA pipelines. Minimizes ISR latency.
Defines async patterns for the embedded team. Establishes interrupt handling standards, event-driven design, DMA strategy.
Understands basic multithreading for embedded systems: RTOS task creation and scheduling, basic semaphore and mutex usage for resource protection, interrupt service routines and thread interaction. Follows team conventions for concurrent firmware design patterns.
Implements concurrent embedded systems: RTOS task management, mutex/semaphore synchronization, priority ceiling protocol. Detects and resolves priority inversion and deadlocks.
Designs concurrent firmware architecture: lock-free algorithms, ISR-safe communications, priority ceiling protocol. Minimizes critical sections.
Defines concurrency standards for the embedded team. Establishes inter-task communication patterns, conducts review of concurrency-critical code.
Embedded Programming 2
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Knows C basics for embedded systems: data types, pointers, register operations. Writes simple drivers under mentor guidance on STM32/ESP32.
Independently writes peripheral drivers in C for STM32/nRF52. Uses volatile, bitmasks, direct register access through CMSIS.
Designs HAL layer in C for MCU families. Optimizes code for Flash/RAM constraints, applies DMA and interrupts for high-performance tasks.
Defines C coding standards for the embedded team. Introduces static analysis (PC-lint, Polyspace), establishes platform porting strategy.
Understands C++ memory management basics for microcontrollers. Writes simple drivers and peripheral access code. Follows coding standards for embedded safety-critical systems.
Applies C++17 for embedded: constexpr computations, type-safe register wrappers, CRTP for HAL. Avoids dynamic allocation and exceptions.
Designs zero-cost abstraction HAL in C++ with templates. Applies compile-time polymorphism, optimizes binary size through LTO and -fno-rtti.
Defines C++ subset for the embedded team. Establishes guidelines for STL usage, templates, memory management on resource-constrained platforms.
Embedded Tools 1
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Uses basic debugging tools: JTAG/SWD through ST-Link, breakpoints in IDE, printf debugging through UART. Analyzes simple bugs.
Applies advanced debugging: ITM trace, SWO viewer, Segger RTT, watchpoints on memory access. Uses oscilloscope for timing analysis.
Designs debug infrastructure: custom fault handlers, core dump extraction, post-mortem analysis. Applies Segger SystemView for RTOS profiling.
Defines debug strategy for the product line. Establishes fault handling standards, logging, remote diagnostics for field devices.
Git & Workflows 1
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Uses Git for embedded: commit, push, pull, basic branching. Understands .gitignore for build artifacts and IDE files.
Applies Git workflow: feature branches, interactive rebase, cherry-pick for hotfixes. Uses git submodules for HAL/SDK dependencies.
Manages complex Git scenarios: monorepo for firmware + tools, git-bisect for regression hunting, Git LFS for binary assets.
Defines Git strategy for the embedded team. Establishes branching model, release tagging, submodule management guidelines.
Hardware Interfaces 3
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Understands the fundamentals of BLE & Wireless: Zigbee, LoRa, WiFi. Applies basic practices in daily work. Follows recommendations from the team and documentation.
Independently develops BLE devices: custom GATT services, bonding/pairing, connection parameter optimization. Analyzes packets through sniffer.
Designs BLE mesh networks and multi-connection architectures. Optimizes power consumption in BLE, implements OTA DFU, integrates BLE 5.3 features.
Defines BLE strategy for the product line. Establishes GATT profile standards, security model, conducts BLE architecture reviews for devices.
Understands GPIO, ADC, DAC operation on MCU. Configures pins through HAL, reads analog values. Uses multimeter for signal verification.
Independently configures GPIO alternate functions, ADC with DMA multi-channel scan, DAC with timer trigger. Calibrates ADC for precise measurements.
Designs analog data acquisition systems: oversampling, digital filtering, ADC calibration pipeline. Optimizes power consumption through GPIO configuration.
Defines analog peripheral standards for the platform. Establishes calibration procedures, conducts analog subsystem reviews.
Understands the fundamentals of SPI / I2C / UART Protocols. Applies basic practices in daily work. Follows recommendations from the team and documentation.
Independently implements SPI/I2C/UART drivers: DMA transfers, error handling, multi-slave bus management. Debugs communication issues using logic analyzer.
Designs high-performance communications: multi-slave SPI with chip select mux, I2C bus recovery, UART with custom protocol and CRC.
Defines communication protocol standards for the platform. Establishes unified driver architecture for SPI/I2C/UART, conducts driver reviews.
IoT Platforms 1
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Understands the fundamentals of MQTT Protocol. Applies basic practices in daily work. Follows recommendations from the team and documentation.
Implements MQTT communications: QoS 1/2, retained messages, last will, topic hierarchy design. Optimizes reconnect and keep-alive for unstable networks.
Designs MQTT architecture for IoT fleet: shared subscriptions, broker bridging, MQTT 5.0 features. Implements TLS and client certificate authentication.
Defines MQTT strategy for IoT platform. Establishes topic naming conventions, QoS policy, security standards for device fleet.
Memory Management 1
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Understands MCU memory model: Flash, RAM, stack, heap. Knows linker script sections (.text, .data, .bss). Monitors memory usage.
Manages memory in embedded systems: static allocation strategies, memory pool implementations, MPU configuration for memory protection. Detects and prevents memory leaks.
Designs memory management strategy: MPU configuration, memory-mapped I/O, scatter-loading, placement in specific RAM sections (CCM, DTCM).
Defines memory management standards for the platform. Establishes memory budgeting approaches, leak detection, MPU protection.
Optimization 2
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Understands latency sources in embedded: interrupt latency, context switch, bus wait states. Measures response time with oscilloscope.
Optimizes latency: interrupt prioritization, code placement in RAM (ITCM), interrupt tail-chaining, cache configuration.
Designs ultra-low latency systems: deterministic ISR, zero-wait-state memory access, DMA chaining, predictable scheduling.
Defines latency optimization standards. Establishes timing budgets for critical paths, worst-case latency analysis methodology.
Understands MCU resource constraints: Flash, RAM, CPU cycles, power. Optimizes binary size through compiler flags (-Os, LTO).
Optimizes resources independently: Flash/RAM usage analysis, power profiling, code size optimization through compiler flags and linker scripts.
Designs resource-efficient firmware: function-level power management, adaptive clock scaling, memory overlay techniques.
Defines resource optimization strategy. Establishes resource budgets (Flash/RAM/power) for embedded products, conducts reviews.
Profiling 1
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Uses basic CPU profiling: DWT cycle counter, GPIO toggle + oscilloscope for measuring function execution time on MCU.
Applies advanced profiling: Segger SystemView for task profiling, ETM trace for instruction-level analysis, hotspot detection.
Designs CPU profiling infrastructure: continuous performance monitoring, automated regression benchmarks, power/performance correlation analysis.
Defines CPU profiling standards for the embedded team. Establishes performance budgets, automated regression alerting.
RTOS & Real-Time 3
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Understands bare-metal development: startup code, linker script, interrupt vector table. Writes simple programs without OS on STM32.
Independently develops bare-metal firmware: PLL configuration, peripheral setup through registers, boot sequence implementation on Cortex-M.
Designs bare-metal architecture for production devices. Implements custom scheduler, power management, watchdog recovery, OTA update mechanism.
Defines bare-metal standards for the product line. Establishes approaches to boot security, hardware abstraction, porting between MCU families.
Understands the difference between hard/soft real-time. Knows task scheduling basics, deadlines and jitter. Measures latency with oscilloscope.
Independently develops real-time systems: priority-based scheduling, deadline monitoring, jitter analysis. Implements watchdog timers and timing constraint verification.
Designs hard real-time systems with guaranteed deadlines. Applies formal timing analysis, optimizes interrupt latency, uses hardware timers.
Defines real-time requirements for the product line. Establishes timing constraint verification methodology, conducts review of time-critical systems.
Understands RTOS concepts: tasks, priorities, semaphores, queues. Creates simple multi-task applications on FreeRTOS under mentor guidance.
Independently develops on RTOS: task decomposition, inter-task communication (queues, semaphores, event groups), priority inversion prevention. Configures FreeRTOS for specific hardware.
Designs RTOS application architecture with guaranteed response time. Optimizes stack allocation, applies priority inversion protection, configures tickless idle.
Defines RTOS strategy for the product line. Establishes task decomposition standards, inter-task communication, conducts architecture reviews.
Unit Testing 1
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Understands basic unit testing for embedded code: CUnit/Unity test framework basics, hardware abstraction layer mocking, simple register value assertions. Follows team patterns for testing firmware modules on host before flashing to target.
Tests embedded code independently: Unity/CMock for C unit tests, test doubles for hardware dependencies, coverage analysis. Integrates tests into CI pipeline.
Designs test architecture for firmware: hardware abstraction for testability, test doubles for peripherals, property-based testing.
Defines testing strategy for the embedded team. Establishes coverage requirements, test pyramid for firmware, CI integration.