Algorithms & Data Structures 2
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Understands O-notation and basic algorithms in embedded context: sorting, searching considering MCU memory constraints. Selects appropriate algorithms.
Applies algorithm optimization for embedded: fixed-point arithmetic, lookup tables instead of computation, loop unrolling. Analyzes time complexity considering cache effects.
Defines algorithmic standards for the embedded platform. Establishes optimized algorithm library, conducts critical path reviews.
Defines enterprise approach to algorithms in embedded. Establishes reusable math/DSP libraries for product lines, mentors architects on optimization.
Knows basic data structures for embedded: arrays, linked lists, queues. Understands dynamic memory limitations on MCU.
Implements data structures for embedded: statically-allocated ring buffers, memory pools, intrusive linked lists. Optimizes for cache locality and deterministic performance.
Defines data structure standards for the embedded platform. Establishes statically-allocated container library, conducts reviews.
Defines enterprise approach to data structures in embedded. Creates unified container library for all MCU platforms across the organization.
CI/CD 1
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Understands CI/CD concepts for embedded development: build, test, deploy for firmware. Uses existing workflows for cross-compilation and hardware-in-the-loop tests. Can add a step for firmware validation. Reads failed build logs for toolchain issues.
Designs CI/CD pipelines from scratch. Configures caching to speed up builds. Uses matrix builds for testing on different versions. Sets up deployment pipelines (staging → production). Works with secrets and environment variables.
Designs CI/CD platform for multiple projects. Creates reusable workflows/templates. Optimizes build time at organization level. Configures security scanning in pipeline. Introduces deployment strategies (blue-green, canary). Integrates with ArgoCD/FluxCD.
Concurrency & Parallelism 2
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Understands async model in embedded: interrupts, callbacks, event-driven architecture. Implements simple ISR handlers on STM32.
Implements async patterns in embedded: interrupt-driven I/O, DMA completion callbacks, event-driven state machines. Manages shared state between ISR and main loop.
Defines async patterns for the embedded team. Establishes interrupt handling standards, event-driven design, DMA strategy.
Defines enterprise async strategy for embedded. Establishes unified event system for all products, mentors leads on async architecture.
Understands basic multithreading for embedded systems: RTOS task creation and scheduling, basic semaphore and mutex usage for resource protection, interrupt service routines and thread interaction. Follows team conventions for concurrent firmware design patterns.
Implements concurrent embedded systems: RTOS task management, mutex/semaphore synchronization, priority ceiling protocol. Detects and resolves priority inversion and deadlocks.
Defines concurrency standards for the embedded team. Establishes inter-task communication patterns, conducts review of concurrency-critical code.
Defines enterprise concurrency strategy for embedded. Establishes reference architecture for multi-core MCU, mentors leads on concurrent design.
Embedded Programming 2
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Knows C basics for embedded systems: data types, pointers, register operations. Writes simple drivers under mentor guidance on STM32/ESP32.
Independently writes peripheral drivers in C for STM32/nRF52. Uses volatile, bitmasks, direct register access through CMSIS.
Defines C coding standards for the embedded team. Introduces static analysis (PC-lint, Polyspace), establishes platform porting strategy.
Shapes C language strategy for the embedded platform: coding standards (MISRA C compliance level), toolchain selection, compiler optimization strategy. Evaluates C vs Rust adoption trade-offs.
Understands C++ memory management basics for microcontrollers. Writes simple drivers and peripheral access code. Follows coding standards for embedded safety-critical systems.
Applies C++17 for embedded: constexpr computations, type-safe register wrappers, CRTP for HAL. Avoids dynamic allocation and exceptions.
Defines C++ subset for the embedded team. Establishes guidelines for STL usage, templates, memory management on resource-constrained platforms.
Shapes C++ adoption strategy for embedded: defines allowed C++ subset per safety level, evaluates compiler support across targets, establishes migration path from C codebases.
Embedded Tools 1
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Uses basic debugging tools: JTAG/SWD through ST-Link, breakpoints in IDE, printf debugging through UART. Analyzes simple bugs.
Applies advanced debugging: ITM trace, SWO viewer, Segger RTT, watchpoints on memory access. Uses oscilloscope for timing analysis.
Defines debug strategy for the product line. Establishes fault handling standards, logging, remote diagnostics for field devices.
Shapes debugging methodology for the organization: standardizes debug tooling across products, establishes remote diagnostics architecture, defines post-mortem analysis procedures for field failures.
Hardware Interfaces 3
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Understands the fundamentals of BLE & Wireless: Zigbee, LoRa, WiFi. Applies basic practices in daily work. Follows recommendations from the team and documentation.
Independently develops BLE devices: custom GATT services, bonding/pairing, connection parameter optimization. Analyzes packets through sniffer.
Defines BLE strategy for the product line. Establishes GATT profile standards, security model, conducts BLE architecture reviews for devices.
Shapes BLE/wireless strategy for IoT products: protocol selection (BLE 5.x, Zigbee, Thread, Matter), interoperability architecture, certification planning. Evaluates emerging wireless standards.
Understands GPIO, ADC, DAC operation on MCU. Configures pins through HAL, reads analog values. Uses multimeter for signal verification.
Independently configures GPIO alternate functions, ADC with DMA multi-channel scan, DAC with timer trigger. Calibrates ADC for precise measurements.
Defines analog peripheral standards for the platform. Establishes calibration procedures, conducts analog subsystem reviews.
Shapes analog/digital interface strategy: defines standard HAL for GPIO/ADC/DAC across MCU families, establishes calibration procedures, designs reference implementations for new hardware platforms.
Understands the fundamentals of SPI / I2C / UART Protocols. Applies basic practices in daily work. Follows recommendations from the team and documentation.
Independently implements SPI/I2C/UART drivers: DMA transfers, error handling, multi-slave bus management. Debugs communication issues using logic analyzer.
Defines communication protocol standards for the platform. Establishes unified driver architecture for SPI/I2C/UART, conducts driver reviews.
Shapes communication bus strategy: defines unified driver architecture across products, establishes bus performance standards, creates reference implementations for new MCU platform bring-up.
Infrastructure as Code 1
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Understands Infrastructure as Code concept and basic Terraform syntax. Can read and modify simple configurations for deploying IoT platform cloud resources.
Configures Terraform for IoT infrastructure: AWS IoT Core provisioning, device fleet management resources, edge computing infrastructure deployment.
Defines Infrastructure as Code standards for IoT ecosystem, including compliance policies and drift detection. Designs multi-regional infrastructure with Terraform for IoT platform fault tolerance.
Shapes IaC strategy for the entire embedded ecosystem, including edge infrastructure and cloud components. Designs self-service platform architecture for teams with automated IoT environment provisioning.
IoT Platforms 1
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Understands the fundamentals of MQTT Protocol. Applies basic practices in daily work. Follows recommendations from the team and documentation.
Implements MQTT communications: QoS 1/2, retained messages, last will, topic hierarchy design. Optimizes reconnect and keep-alive for unstable networks.
Defines MQTT strategy for IoT platform. Establishes topic naming conventions, QoS policy, security standards for device fleet.
Shapes MQTT/messaging strategy for IoT platform: broker architecture, protocol versioning, security standards for device fleet. Evaluates alternatives (AMQP, DDS) for specific use cases.
Memory Management 1
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Understands MCU memory model: Flash, RAM, stack, heap. Knows linker script sections (.text, .data, .bss). Monitors memory usage.
Manages memory in embedded systems: static allocation strategies, memory pool implementations, MPU configuration for memory protection. Detects and prevents memory leaks.
Defines memory management standards for the platform. Establishes memory budgeting approaches, leak detection, MPU protection.
Defines enterprise memory management strategy. Establishes unified memory model for all MCU platforms, mentors leads on memory optimization.
Optimization 2
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Understands latency sources in embedded: interrupt latency, context switch, bus wait states. Measures response time with oscilloscope.
Optimizes latency: interrupt prioritization, code placement in RAM (ITCM), interrupt tail-chaining, cache configuration.
Defines latency optimization standards. Establishes timing budgets for critical paths, worst-case latency analysis methodology.
Shapes latency optimization strategy: defines timing budget methodology, establishes worst-case execution time analysis standards, creates latency regression detection across product lines.
Understands MCU resource constraints: Flash, RAM, CPU cycles, power. Optimizes binary size through compiler flags (-Os, LTO).
Optimizes resources independently: Flash/RAM usage analysis, power profiling, code size optimization through compiler flags and linker scripts.
Defines resource optimization strategy. Establishes resource budgets (Flash/RAM/power) for embedded products, conducts reviews.
Shapes resource optimization strategy across product lines: defines resource budgeting methodology (Flash/RAM/power/cost), establishes optimization review process, drives hardware selection decisions.
RTOS & Real-Time 3
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Understands bare-metal development: startup code, linker script, interrupt vector table. Writes simple programs without OS on STM32.
Independently develops bare-metal firmware: PLL configuration, peripheral setup through registers, boot sequence implementation on Cortex-M.
Defines bare-metal standards for the product line. Establishes approaches to boot security, hardware abstraction, porting between MCU families.
Shapes bare-metal development strategy: boot architecture standards, hardware abstraction layer design, silicon vendor evaluation criteria. Defines bring-up procedures for new MCU platforms.
Understands the difference between hard/soft real-time. Knows task scheduling basics, deadlines and jitter. Measures latency with oscilloscope.
Independently develops real-time systems: priority-based scheduling, deadline monitoring, jitter analysis. Implements watchdog timers and timing constraint verification.
Defines real-time requirements for the product line. Establishes timing constraint verification methodology, conducts review of time-critical systems.
Shapes real-time systems strategy: defines timing verification methodology, establishes WCET analysis standards, drives certification for safety-critical real-time systems (DO-178C, IEC 61508).
Understands RTOS concepts: tasks, priorities, semaphores, queues. Creates simple multi-task applications on FreeRTOS under mentor guidance.
Independently develops on RTOS: task decomposition, inter-task communication (queues, semaphores, event groups), priority inversion prevention. Configures FreeRTOS for specific hardware.
Defines RTOS strategy for the product line. Establishes task decomposition standards, inter-task communication, conducts architecture reviews.
Shapes RTOS strategy for the organization: RTOS selection criteria (FreeRTOS vs Zephyr vs custom), task architecture standards, certification path for safety-critical RTOS usage.